mirror of https://github.com/YosysHQ/yosys.git
14 lines
506 B
Plaintext
14 lines
506 B
Plaintext
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read_verilog ../common/tribuf.v
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hierarchy -top tristate
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proc
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tribuf
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flatten
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synth
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equiv_opt -assert -map +/gatemate/cells_sim.v -map +/simcells.v synth_gatemate # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd tristate # Constrain all select calls below inside the top module
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select -assert-count 2 t:CC_IBUF
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select -assert-count 1 t:CC_LUT1
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select -assert-count 1 t:CC_TOBUF
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select -assert-none t:CC_IBUF t:CC_LUT1 t:CC_TOBUF %% t:* %D
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