mirror of https://github.com/YosysHQ/yosys.git
11 lines
448 B
Plaintext
11 lines
448 B
Plaintext
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read_verilog ../common/counter.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -assert -multiclock -map +/machxo2/cells_sim.v synth_machxo2 -ccu2 -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 4 t:CCU2D
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select -assert-count 8 t:TRELLIS_FF
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select -assert-none t:CCU2D t:TRELLIS_FF %% t:* %D
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