mirror of https://github.com/YosysHQ/yosys.git
19 lines
258 B
Verilog
19 lines
258 B
Verilog
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module top(
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input wire x,
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output reg y
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);
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localparam I = 1;
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genvar i;
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generate
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for (i = 0; i < 1; i = i + 1) begin : blk
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wire [i:i] z = x;
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end
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endgenerate
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always @* begin
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case (blk[I - 1].z)
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1: y = 0;
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0: y = 1;
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endcase
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end
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endmodule
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