mirror of https://github.com/YosysHQ/yosys.git
77 lines
1.3 KiB
Systemverilog
77 lines
1.3 KiB
Systemverilog
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module TopModule(
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input logic clk,
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input logic rst,
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input logic [1:0] sig,
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output logic [1:0] sig_out);
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MyInterface #(.WIDTH(4)) MyInterfaceInstance();
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SubModule1 u_SubModule1 (
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.clk(clk),
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.rst(rst),
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.u_MyInterface(MyInterfaceInstance),
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.sig (sig)
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);
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assign sig_out = MyInterfaceInstance.mysig_out;
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assign MyInterfaceInstance.setting = 1;
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assign MyInterfaceInstance.other_setting[2:0] = 3'b101;
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endmodule
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interface MyInterface #(
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parameter WIDTH = 3)(
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);
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logic setting;
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logic [WIDTH-1:0] other_setting;
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logic [1:0] mysig_out;
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endinterface
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module SubModule1(
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input logic clk,
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input logic rst,
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MyInterface u_MyInterface,
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input logic [1:0] sig
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);
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always_ff @(posedge clk or posedge rst)
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if(rst)
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u_MyInterface.mysig_out <= 0;
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else begin
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if(u_MyInterface.setting)
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u_MyInterface.mysig_out <= sig;
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else
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u_MyInterface.mysig_out <= ~sig;
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end
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MyInterface #(.WIDTH(22)) MyInterfaceInstanceInSub();
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SubModule2 u_SubModule2 (
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.clk(clk),
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.rst(rst),
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.u_MyInterfaceInSub2(u_MyInterface),
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.sig (sig)
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);
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endmodule
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module SubModule2(
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input logic clk,
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input logic rst,
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MyInterface u_MyInterfaceInSub2,
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input logic [1:0] sig
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);
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endmodule
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