2023-04-04 04:18:24 -05:00
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r
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proc
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memory -nomap
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2023-08-29 03:21:58 -05:00
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equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2
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2023-04-04 04:18:24 -05:00
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w1r
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select -assert-count 20 t:LUT4
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select -assert-count 8 t:TRELLIS_DPR16X4
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select -assert-count 8 t:TRELLIS_FF
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select -assert-none t:LUT4 t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D
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