2020-11-26 20:58:20 -06:00
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read_verilog ../common/add_sub.v
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hierarchy -top top
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proc
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2023-08-25 04:10:20 -05:00
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equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
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2020-11-26 20:58:20 -06:00
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 10 t:LUT4
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2023-03-18 12:12:02 -05:00
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select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
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