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What is Yosys
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=============
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2023-12-07 15:46:05 -06:00
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Yosys began as a BSc thesis project by Claire Wolf intended to support synthesis
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for a CGRA (coarse-grained reconfigurable architecture). It then expanded into
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more general infrastructure for research on synthesis.
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Modern Yosys has full support for the synthesizable subset of Verilog-2005 and
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has been described as "the GCC of hardware synthesis." Freely available and
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`open source`_, Yosys finds use across hobbyist and commercial applications as
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well as academic.
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.. _open source: https://github.com/YosysHQ/yosys
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.. note:: Yosys is released under the ISC License:
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A permissive license lets people do anything with your code with proper
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attribution and without warranty. The ISC license is functionally equivalent
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to the BSD 2-Clause and MIT licenses, removing some language that is no
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longer necessary.
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Together with the place and route tool `nextpnr`_, Yosys can be used to program
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some FPGAs with a fully end-to-end open source flow (Lattice iCE40 and ECP5). It
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also does the synthesis portion for the `OpenLane flow`_, targeting the SkyWater
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130nm open source PDK for fully open source ASIC design. Yosys can also do
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formal verification with backends for solver formats like `SMT2`_.
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.. _nextpnr: https://github.com/YosysHQ/nextpnr
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.. _OpenLane flow: https://github.com/The-OpenROAD-Project/OpenLane
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.. _SMT2: https://smtlib.cs.uiowa.edu/
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Yosys, and the accompanying Open Source EDA ecosystem, is currently maintained
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by `Yosys Headquarters`_, with many of the core developers employed by `YosysHQ
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GmbH`_. A commercial extension, `Tabby CAD Suite`_, includes the Verific
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frontend for industry-grade SystemVerilog and VHDL support, formal verification
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with SVA, and formal apps.
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.. _Yosys Headquarters: https://github.com/YosysHQ
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.. _YosysHQ GmbH: https://www.yosyshq.com/about
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.. _Tabby CAD Suite: https://www.yosyshq.com/tabby-cad-datasheet
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.. figure:: /_static/logo.png
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:class: width-helper
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2023-08-02 16:20:24 -05:00
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What you can do with Yosys
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--------------------------
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- Read and process (most of) modern Verilog-2005 code
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- Perform all kinds of operations on netlist (RTL, Logic, Gate)
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- Perform logic optimizations and gate mapping with ABC
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Typical applications for Yosys
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Synthesis of final production designs
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- Pre-production synthesis (trial runs before investing in other tools)
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- Conversion of full-featured Verilog to simple Verilog
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- Conversion of Verilog to other formats (BLIF, BTOR, etc)
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- Demonstrating synthesis algorithms (e.g. for educational purposes)
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- Framework for experimenting with new algorithms
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- Framework for building custom flows (Not limited to synthesis but also formal
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verification, reverse engineering, ...)
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Things you can't do
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~~~~~~~~~~~~~~~~~~~
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- Process high-level languages such as C/C++/SystemC
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- Create physical layouts (place&route)
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- Check out `nextpnr`_ for that
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.. _nextpnr: https://github.com/YosysHQ/nextpnr
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The Yosys family
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----------------
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As mentioned above, `YosysHQ`_ maintains not just Yosys but an entire family of
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tools built around it.
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.. _YosysHQ: https://github.com/YosysHQ
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.. TODO:: Yosys family descriptions
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In no particular order:
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- SBY for formal verification
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- https://github.com/YosysHQ/sby
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- https://yosyshq.readthedocs.io/projects/sby
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- EQY for equivalence checking
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- https://github.com/YosysHQ/eqy
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- https://yosyshq.readthedocs.io/projects/eqy
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- MCY for mutation coverage
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- https://github.com/YosysHQ/mcy
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- https://yosyshq.readthedocs.io/projects/mcy
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- SCY for deep formal traces
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- https://github.com/YosysHQ/scy
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The original thesis abstract
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----------------------------
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The first version of the Yosys documentation was published as a bachelor thesis
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at the Vienna University of Technology :cite:p:`BACC`.
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:Abstract:
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Most of today's digital design is done in HDL code (mostly Verilog or
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VHDL) and with the help of HDL synthesis tools.
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In special cases such as synthesis for coarse-grain cell libraries or
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when testing new synthesis algorithms it might be necessary to write a
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custom HDL synthesis tool or add new features to an existing one. In
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these cases the availability of a Free and Open Source (FOSS) synthesis
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tool that can be used as basis for custom tools would be helpful.
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In the absence of such a tool, the Yosys Open SYnthesis Suite (Yosys)
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was developed. This document covers the design and implementation of
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this tool. At the moment the main focus of Yosys lies on the high-level
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aspects of digital synthesis. The pre-existing FOSS logic-synthesis tool
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ABC is used by Yosys to perform advanced gate-level optimizations.
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An evaluation of Yosys based on real-world designs is included. It is
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shown that Yosys can be used as-is to synthesize such designs. The
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results produced by Yosys in this tests where successfully verified
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using formal verification and are comparable in quality to the results
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produced by a commercial synthesis tool.
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Yosys is a Verilog HDL synthesis tool. This means that it takes a behavioural
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design description as input and generates an RTL, logical gate or physical gate
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level description of the design as output. Yosys' main strengths are behavioural
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and RTL synthesis. A wide range of commands (synthesis passes) exist within
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Yosys that can be used to perform a wide range of synthesis tasks within the
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domain of behavioural, rtl and logic synthesis. Yosys is designed to be
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extensible and therefore is a good basis for implementing custom synthesis tools
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for specialised tasks.
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.. figure:: /_images/primer/levels_of_abstraction.*
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:class: width-helper
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:name: fig:Levels_of_abstraction
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Where Yosys exists in the layers of abstraction
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Benefits of open source HDL synthesis
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Cost (also applies to ``free as in free beer`` solutions):
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Today the cost for a mask set in 180nm technology is far less than
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the cost for the design tools needed to design the mask layouts. Open Source
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ASIC flows are an important enabler for ASIC-level Open Source Hardware.
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- Availability and Reproducibility:
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If you are a researcher who is publishing, you want to use tools that everyone
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else can also use. Even if most universities have access to all major
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commercial tools, you usually do not have easy access to the version that was
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used in a research project a couple of years ago. With Open Source tools you
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can even release the source code of the tool you have used alongside your data.
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- Framework:
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Yosys is not only a tool. It is a framework that can be used as basis for other
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developments, so researchers and hackers alike do not need to re-invent the
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basic functionality. Extensibility was one of Yosys' design goals.
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- All-in-one:
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Because of the framework characteristics of Yosys, an increasing number of features
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become available in one tool. Yosys not only can be used for circuit synthesis but
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also for formal equivalence checking, SAT solving, and for circuit analysis, to
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name just a few other application domains. With proprietary software one needs to
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learn a new tool for each of these applications.
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- Educational Tool:
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Proprietary synthesis tools are at times very secretive about their inner
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workings. They often are ``black boxes``. Yosys is very open about its
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internals and it is easy to observe the different steps of synthesis.
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.. note:: Yosys is licensed under the ISC license:
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Permission to use, copy, modify, and/or distribute this software for any
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purpose with or without fee is hereby granted, provided that the above
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copyright notice and this permission notice appear in all copies.
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History of Yosys
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~~~~~~~~~~~~~~~~
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.. todo:: Consider a less academic version of the History of Yosys
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A Hardware Description Language (HDL) is a computer language used to describe
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circuits. A HDL synthesis tool is a computer program that takes a formal
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description of a circuit written in an HDL as input and generates a netlist that
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implements the given circuit as output.
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Currently the most widely used and supported HDLs for digital circuits are
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Verilog :cite:p:`Verilog2005,VerilogSynth` and :abbr:`VHDL (VHSIC HDL, where
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VHSIC is an acronym for Very-High-Speed Integrated Circuits)`
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:cite:p:`VHDL,VHDLSynth`. Both HDLs are used for test and verification purposes
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as well as logic synthesis, resulting in a set of synthesizable and a set of
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non-synthesizable language features. In this document we only look at the
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synthesizable subset of the language features.
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In recent work on heterogeneous coarse-grain reconfigurable logic
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:cite:p:`intersynth` the need for a custom application-specific HDL synthesis
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tool emerged. It was soon realised that a synthesis tool that understood Verilog
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or VHDL would be preferred over a synthesis tool for a custom HDL. Given an
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existing Verilog or VHDL front end, the work for writing the necessary
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additional features and integrating them in an existing tool can be estimated to
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be about the same as writing a new tool with support for a minimalistic custom
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HDL.
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The proposed custom HDL synthesis tool should be licensed under a Free and Open
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Source Software (FOSS) licence. So an existing FOSS Verilog or VHDL synthesis
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tool would have been needed as basis to build upon. The main advantages of
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choosing Verilog or VHDL is the ability to synthesize existing HDL code and to
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mitigate the requirement for circuit-designers to learn a new language. In order
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to take full advantage of any existing FOSS Verilog or VHDL tool, such a tool
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would have to provide a feature-complete implementation of the synthesizable HDL
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subset.
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Basic RTL synthesis is a well understood field :cite:p:`LogicSynthesis`. Lexing,
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parsing and processing of computer languages :cite:p:`Dragonbook` is a
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thoroughly researched field. All the information required to write such tools
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has been openly available for a long time, and it is therefore likely that a
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FOSS HDL synthesis tool with a feature-complete Verilog or VHDL front end must
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exist which can be used as a basis for a custom RTL synthesis tool.
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Due to the author's preference for Verilog over VHDL it was decided early on to
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go for Verilog instead of VHDL [#]_. So the existing FOSS Verilog synthesis
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tools were evaluated. The results of this evaluation are utterly devastating.
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Therefore a completely new Verilog synthesis tool was implemented and is
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recommended as basis for custom synthesis tools. This is the tool that is
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discussed in this document.
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.. [#]
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A quick investigation into FOSS VHDL tools yielded similar grim results for
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FOSS VHDL synthesis tools.
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