mirror of https://github.com/YosysHQ/yosys.git
14 lines
145 B
Plaintext
14 lines
145 B
Plaintext
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read_verilog << EOF
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module top(...);
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input A1, A2, B, S;
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output O;
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assign O = S ? (A1 & B) : (A2 & B);
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endmodule
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EOF
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simplemap
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opt_share
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dump
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