mirror of https://github.com/YosysHQ/yosys.git
24 lines
306 B
Plaintext
24 lines
306 B
Plaintext
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read_ilang << EOF
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module \top
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wire width 4 input 1 \A
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wire output 2 \Y
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cell $lut \lut
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parameter \LUT 16'1111110011000000
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parameter \WIDTH 4
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connect \A \A
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connect \Y \Y
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end
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end
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EOF
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equiv_opt -assert opt_lut_ins
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design -load postopt
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select -assert-count 1 t:$lut r:WIDTH=3 %i
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