mirror of https://github.com/YosysHQ/yosys.git
29 lines
517 B
Plaintext
29 lines
517 B
Plaintext
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read_verilog -icells <<EOF
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module test(a, b, s, y);
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input a, b, s;
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output y;
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wire f, g;
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$_ANDNOT_ g1(.A(a), .B(b), .Y(f));
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$_ANDNOT_ g2(.A(b), .B(a), .Y(g));
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$_MUX_ m(.A(f), .B(g), .S(s), .Y(y));
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endmodule
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EOF
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equiv_opt -assert opt_share
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design -reset
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read_verilog -icells <<EOF
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module test(a, b, s, y);
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input a, b, s;
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output y;
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wire f, g;
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$_ORNOT_ g1(.A(a), .B(b), .Y(f));
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$_ORNOT_ g2(.A(b), .B(a), .Y(g));
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$_MUX_ m(.A(f), .B(g), .S(s), .Y(y));
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endmodule
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EOF
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equiv_opt -assert opt_share
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