mirror of https://github.com/YosysHQ/yosys.git
14 lines
146 B
Verilog
14 lines
146 B
Verilog
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module if_else();
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reg dff;
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wire clk,din,reset;
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always @ (posedge clk)
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if (reset) begin
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dff <= 0;
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end else begin
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dff <= din;
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end
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endmodule
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