2023-12-06 22:14:21 -06:00
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Memory handling
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===============
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The :cmd:ref:`memory` command
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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In the RTL netlist, memory reads and writes are individual cells. This makes
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consolidating the number of ports for a memory easier. The :cmd:ref:`memory`
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pass transforms memories to an implementation. Per default that is logic for
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address decoders and registers. It also is a macro command that calls the other
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common ``memory_*`` passes in a sensible order:
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2024-01-23 15:29:40 -06:00
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.. literalinclude:: /code_examples/macro_commands/memory.ys
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:language: yoscrypt
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:start-after: #end:
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:caption: Passes called by :cmd:ref:`memory`
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.. todo:: Make ``memory_*`` notes less quick
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Some quick notes:
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2024-01-23 15:29:40 -06:00
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- :cmd:ref:`memory_dff` merges registers into the memory read- and write cells.
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- :cmd:ref:`memory_collect` collects all read and write cells for a memory and
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transforms them into one multi-port memory cell.
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- :cmd:ref:`memory_map` takes the multi-port memory cell and transforms it to
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address decoder logic and registers.
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For more information about :cmd:ref:`memory`, such as disabling certain sub
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commands, see :doc:`/cmd/memory`.
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Example
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-------
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.. todo:: describe ``memory`` images
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.. figure:: /_images/code_examples/synth_flow/memory_01.*
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:class: width-helper
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.. literalinclude:: /code_examples/synth_flow/memory_01.ys
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:language: yoscrypt
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:caption: ``docs/source/code_examples/synth_flow/memory_01.ys``
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.. literalinclude:: /code_examples/synth_flow/memory_01.v
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:language: verilog
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:caption: ``docs/source/code_examples/synth_flow/memory_01.v``
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.. figure:: /_images/code_examples/synth_flow/memory_02.*
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:class: width-helper
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.. literalinclude:: /code_examples/synth_flow/memory_02.v
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:language: verilog
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:caption: ``docs/source/code_examples/synth_flow/memory_02.v``
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.. literalinclude:: /code_examples/synth_flow/memory_02.ys
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:language: yoscrypt
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:caption: ``docs/source/code_examples/synth_flow/memory_02.ys``
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.. _memory_map:
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Memory mapping
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^^^^^^^^^^^^^^
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2023-12-11 17:05:45 -06:00
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.. TODO:: :cmd:ref:`memory_libmap` description
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Usually it is preferred to use architecture-specific RAM resources for memory.
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For example:
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.. code-block:: yoscrypt
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memory -nomap
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memory_libmap -lib my_memory_map.txt
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techmap -map my_memory_map.v
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memory_map
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Supported memory patterns
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^^^^^^^^^^^^^^^^^^^^^^^^^
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Note that not all supported patterns are included in this document, of
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particular note is that combinations of multiple patterns should generally work.
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For example, `wbe`_ could be used in conjunction with any of the simple dual
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port (SDP) models. In general if a hardware memory definition does not support
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a given configuration, additional logic will be instantiated to guarantee
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behaviour is consistent with simulation.
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See also: `passes/memory/memlib.md <https://github.com/YosysHQ/yosys/blob/master/passes/memory/memlib.md>`_
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Notes
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-----
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Memory kind selection
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~~~~~~~~~~~~~~~~~~~~~
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The memory inference code will automatically pick target memory primitive based on memory geometry
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and features used. Depending on the target, there can be up to four memory primitive classes
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available for selection:
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- FF RAM (aka logic): no hardware primitive used, memory lowered to a bunch of FFs and multiplexers
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- Can handle arbitrary number of write ports, as long as all write ports are in the same clock domain
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- Can handle arbitrary number and kind of read ports
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- LUT RAM (aka distributed RAM): uses LUT storage as RAM
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- Supported on most FPGAs (with notable exception of ice40)
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- Usually has one synchronous write port, one or more asynchronous read ports
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- Small
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- Will never be used for ROMs (lowering to plain LUTs is always better)
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- Block RAM: dedicated memory tiles
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- Supported on basically all FPGAs
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- Supports only synchronous reads
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- Two ports with separate clocks
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- Usually supports true dual port (with notable exception of ice40 that only supports SDP)
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- Usually supports asymmetric memories and per-byte write enables
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- Several kilobits in size
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- Huge RAM:
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- Only supported on several targets:
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- Some Xilinx UltraScale devices (UltraRAM)
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- Two ports, both with mutually exclusive synchronous read and write
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- Single clock
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- Initial data must be all-0
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- Some ice40 devices (SPRAM)
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- Single port with mutually exclusive synchronous read and write
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- Does not support initial data
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- Nexus (large RAM)
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- Two ports, both with mutually exclusive synchronous read and write
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- Single clock
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- Will not be automatically selected by memory inference code, needs explicit opt-in via
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ram_style attribute
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In general, you can expect the automatic selection process to work roughly like this:
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- If any read port is asynchronous, only LUT RAM (or FF RAM) can be used.
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- If there is more than one write port, only block RAM can be used, and this needs to be a
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hardware-supported true dual port pattern
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- … unless all write ports are in the same clock domain, in which case FF RAM can also be used,
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but this is generally not what you want for anything but really small memories
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- Otherwise, either FF RAM, LUT RAM, or block RAM will be used, depending on memory size
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This process can be overridden by attaching a ram_style attribute to the memory:
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- `(* ram_style = "logic" *)` selects FF RAM
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- `(* ram_style = "distributed" *)` selects LUT RAM
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- `(* ram_style = "block" *)` selects block RAM
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- `(* ram_style = "huge" *)` selects huge RAM
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It is an error if this override cannot be realized for the given target.
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Many alternate spellings of the attribute are also accepted, for compatibility with other software.
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Initial data
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~~~~~~~~~~~~
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Most FPGA targets support initializing all kinds of memory to user-provided values. If explicit
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initialization is not used the initial memory value is undefined. Initial data can be provided by
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either initial statements writing memory cells one by one of ``$readmemh`` or ``$readmemb`` system
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tasks. For an example pattern, see `sr_init`_.
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.. _wbe:
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Write port with byte enables
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Byte enables can be used with any supported pattern
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- To ensure that multiple writes will be merged into one port, they need to have disjoint bit
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ranges, have the same address, and the same clock
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- Any write enable granularity will be accepted (down to per-bit write enables), but using smaller
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granularity than natively supported by the target is very likely to be inefficient (eg. using
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4-bit bytes on ECP5 will result in either padding the bytes with 5 dummy bits to native 9-bit
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units or splitting the RAM into two block RAMs)
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.. code:: verilog
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reg [31 : 0] mem [2**ADDR_WIDTH - 1 : 0];
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always @(posedge clk) begin
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if (write_enable[0])
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mem[write_addr][7:0] <= write_data[7:0];
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if (write_enable[1])
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mem[write_addr][15:8] <= write_data[15:8];
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if (write_enable[2])
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mem[write_addr][23:16] <= write_data[23:16];
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if (write_enable[3])
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mem[write_addr][31:24] <= write_data[31:24];
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if (read_enable)
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read_data <= mem[read_addr];
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end
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Simple dual port (SDP) memory patterns
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--------------------------------------
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2023-12-06 22:14:21 -06:00
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.. todo:: assorted enables, e.g. cen, wen+ren
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2023-06-18 19:05:51 -05:00
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Asynchronous-read SDP
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~~~~~~~~~~~~~~~~~~~~~
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- This will result in LUT RAM on supported targets
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.. code:: verilog
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reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0];
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always @(posedge clk)
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if (write_enable)
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mem[write_addr] <= write_data;
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assign read_data = mem[read_addr];
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Synchronous SDP with clock domain crossing
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Will result in block RAM or LUT RAM depending on size
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- No behavior guarantees in case of simultaneous read and write to the same address
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.. code:: verilog
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reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0];
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always @(posedge write_clk) begin
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if (write_enable)
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mem[write_addr] <= write_data;
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end
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always @(posedge read_clk) begin
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if (read_enable)
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read_data <= mem[read_addr];
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end
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Synchronous SDP read first
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~~~~~~~~~~~~~~~~~~~~~~~~~~
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- The read and write parts can be in the same or different processes.
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- Will result in block RAM or LUT RAM depending on size
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- As long as the same clock is used for both, yosys will ensure read-first behavior. This may
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require extra circuitry on some targets for block RAM. If this is not necessary, use one of the
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patterns below.
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.. code:: verilog
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reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0];
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always @(posedge clk) begin
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if (write_enable)
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mem[write_addr] <= write_data;
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if (read_enable)
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read_data <= mem[read_addr];
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end
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2024-01-07 21:59:03 -06:00
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.. _no_rw_check:
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2023-04-04 04:31:26 -05:00
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Synchronous SDP with undefined collision behavior
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Like above, but the read value is undefined when read and write ports target the same address in
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the same cycle
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.. code:: verilog
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reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0];
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always @(posedge clk) begin
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if (write_enable)
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mem[write_addr] <= write_data;
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if (read_enable) begin
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read_data <= mem[read_addr];
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if (write_enable && read_addr == write_addr)
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// this if block
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read_data <= 'x;
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end
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end
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- Or below, using the no_rw_check attribute
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.. code:: verilog
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(* no_rw_check *)
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reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0];
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always @(posedge clk) begin
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if (write_enable)
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mem[write_addr] <= write_data;
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if (read_enable)
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read_data <= mem[read_addr];
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end
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2023-12-06 22:14:21 -06:00
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.. _sdp_wf:
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2023-04-04 04:31:26 -05:00
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Synchronous SDP with write-first behavior
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Will result in block RAM or LUT RAM depending on size
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- May use additional circuitry for block RAM if write-first is not natively supported. Will always
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use additional circuitry for LUT RAM.
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.. code:: verilog
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reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0];
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always @(posedge clk) begin
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if (write_enable)
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mem[write_addr] <= write_data;
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if (read_enable) begin
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read_data <= mem[read_addr];
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if (write_enable && read_addr == write_addr)
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read_data <= write_data;
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end
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end
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Synchronous SDP with write-first behavior (alternate pattern)
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- This pattern is supported for compatibility, but is much less flexible than the above
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.. code:: verilog
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2023-09-18 18:26:57 -05:00
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reg [ADDR_WIDTH - 1 : 0] read_addr_reg;
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reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0];
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always @(posedge clk) begin
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if (write_enable)
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mem[write_addr] <= write_data;
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read_addr_reg <= read_addr;
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end
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assign read_data = mem[read_addr_reg];
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2023-06-18 19:05:51 -05:00
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Single-port RAM memory patterns
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-------------------------------
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2023-04-04 04:31:26 -05:00
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Asynchronous-read single-port RAM
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Will result in single-port LUT RAM on supported targets
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.. code:: verilog
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reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0];
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always @(posedge clk)
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if (write_enable)
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mem[addr] <= write_data;
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assign read_data = mem[addr];
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Synchronous single-port RAM with mutually exclusive read/write
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Will result in single-port block RAM or LUT RAM depending on size
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- This is the correct pattern to infer ice40 SPRAM (with manual ram_style selection)
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- On targets that don't support read/write block RAM ports (eg. ice40), will result in SDP block RAM instead
|
|
|
|
- For block RAM, will use "NO_CHANGE" mode if available
|
|
|
|
|
|
|
|
.. code:: verilog
|
|
|
|
|
|
|
|
reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0];
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if (write_enable)
|
|
|
|
mem[addr] <= write_data;
|
|
|
|
else if (read_enable)
|
|
|
|
read_data <= mem[addr];
|
|
|
|
end
|
|
|
|
|
|
|
|
Synchronous single-port RAM with read-first behavior
|
|
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
|
|
|
|
- Will only result in single-port block RAM when read-first behavior is natively supported;
|
|
|
|
otherwise, SDP RAM with additional circuitry will be used
|
|
|
|
- Many targets (Xilinx, ECP5, …) can only natively support read-first/write-first single-port RAM
|
|
|
|
(or TDP RAM) where the write_enable signal implies the read_enable signal (ie. can never write
|
|
|
|
without reading). The memory inference code will run a simple SAT solver on the control signals to
|
|
|
|
determine if this is the case, and insert emulation circuitry if it cannot be easily proven.
|
|
|
|
|
|
|
|
.. code:: verilog
|
|
|
|
|
|
|
|
reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0];
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if (write_enable)
|
|
|
|
mem[addr] <= write_data;
|
|
|
|
if (read_enable)
|
|
|
|
read_data <= mem[addr];
|
|
|
|
end
|
|
|
|
|
|
|
|
Synchronous single-port RAM with write-first behavior
|
|
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
|
|
|
|
- Will result in single-port block RAM or LUT RAM when supported
|
|
|
|
- Block RAMs will require extra circuitry if write-first behavior not natively supported
|
|
|
|
|
|
|
|
.. code:: verilog
|
|
|
|
|
|
|
|
reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0];
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if (write_enable)
|
|
|
|
mem[addr] <= write_data;
|
|
|
|
if (read_enable)
|
|
|
|
if (write_enable)
|
|
|
|
read_data <= write_data;
|
|
|
|
else
|
|
|
|
read_data <= mem[addr];
|
|
|
|
end
|
|
|
|
|
2023-12-06 22:14:21 -06:00
|
|
|
.. _sr_init:
|
|
|
|
|
2023-04-04 04:31:26 -05:00
|
|
|
Synchronous read port with initial value
|
|
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
|
|
|
|
- Initial read port values can be combined with any other supported pattern
|
|
|
|
- If block RAM is used and initial read port values are not natively supported by the target, small
|
|
|
|
emulation circuit will be inserted
|
|
|
|
|
|
|
|
.. code:: verilog
|
|
|
|
|
|
|
|
reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0];
|
|
|
|
reg [DATA_WIDTH - 1 : 0] read_data;
|
|
|
|
initial read_data = 'h1234;
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if (write_enable)
|
|
|
|
mem[write_addr] <= write_data;
|
|
|
|
if (read_enable)
|
|
|
|
read_data <= mem[read_addr];
|
|
|
|
end
|
|
|
|
|
2023-06-18 19:05:51 -05:00
|
|
|
Read register reset patterns
|
|
|
|
----------------------------
|
2023-04-04 04:31:26 -05:00
|
|
|
|
2023-06-18 19:05:51 -05:00
|
|
|
Resets can be combined with any other supported pattern (except that synchronous reset and
|
|
|
|
asynchronous reset cannot both be used on a single read port). If block RAM is used and the
|
|
|
|
selected reset (synchronous or asynchronous) is used but not natively supported by the target, small
|
|
|
|
emulation circuitry will be inserted.
|
|
|
|
|
|
|
|
Synchronous reset, reset priority over enable
|
|
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
2023-04-04 04:31:26 -05:00
|
|
|
|
|
|
|
.. code:: verilog
|
|
|
|
|
|
|
|
reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0];
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if (write_enable)
|
|
|
|
mem[write_addr] <= write_data;
|
|
|
|
|
|
|
|
if (read_reset)
|
2023-09-18 18:26:57 -05:00
|
|
|
read_data <= 'h1234;
|
2023-04-04 04:31:26 -05:00
|
|
|
else if (read_enable)
|
|
|
|
read_data <= mem[read_addr];
|
|
|
|
end
|
|
|
|
|
2023-06-18 19:05:51 -05:00
|
|
|
Synchronous reset, enable priority over reset
|
|
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
2023-04-04 04:31:26 -05:00
|
|
|
|
|
|
|
.. code:: verilog
|
|
|
|
|
|
|
|
reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0];
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if (write_enable)
|
|
|
|
mem[write_addr] <= write_data;
|
|
|
|
if (read_enable)
|
|
|
|
if (read_reset)
|
|
|
|
read_data <= 'h1234;
|
|
|
|
else
|
|
|
|
read_data <= mem[read_addr];
|
|
|
|
end
|
|
|
|
|
|
|
|
Synchronous read port with asynchronous reset
|
|
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
|
|
|
|
.. code:: verilog
|
|
|
|
|
|
|
|
reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0];
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if (write_enable)
|
|
|
|
mem[write_addr] <= write_data;
|
|
|
|
end
|
|
|
|
|
2023-09-18 18:26:57 -05:00
|
|
|
always @(posedge clk, posedge read_reset) begin
|
|
|
|
if (read_reset)
|
2023-04-04 04:31:26 -05:00
|
|
|
read_data <= 'h1234;
|
|
|
|
else if (read_enable)
|
|
|
|
read_data <= mem[read_addr];
|
|
|
|
end
|
|
|
|
|
2023-06-18 19:05:51 -05:00
|
|
|
Asymmetric memory patterns
|
|
|
|
--------------------------
|
2023-04-04 04:31:26 -05:00
|
|
|
|
|
|
|
To construct an asymmetric memory (memory with read/write ports of differing widths):
|
|
|
|
|
|
|
|
- Declare the memory with the width of the narrowest intended port
|
|
|
|
- Split all wide ports into multiple narrow ports
|
|
|
|
- To ensure the wide ports will be correctly merged:
|
|
|
|
|
|
|
|
- For the address, use a concatenation of actual address in the high bits and a constant in the
|
|
|
|
low bits
|
|
|
|
- Ensure the actual address is identical for all ports belonging to the wide port
|
|
|
|
- Ensure that clock is identical
|
|
|
|
- For read ports, ensure that enable/reset signals are identical (for write ports, the enable
|
|
|
|
signal may vary — this will result in using the byte enable functionality)
|
|
|
|
|
2023-06-18 19:05:51 -05:00
|
|
|
Asymmetric memory is supported on all targets, but may require emulation circuitry where not
|
|
|
|
natively supported. Note that when the memory is larger than the underlying block RAM primitive,
|
|
|
|
hardware asymmetric memory support is likely not to be used even if present as it is more expensive.
|
2023-04-04 04:31:26 -05:00
|
|
|
|
2023-12-06 22:14:21 -06:00
|
|
|
.. _wide_sr:
|
|
|
|
|
2023-06-18 19:05:51 -05:00
|
|
|
Wide synchronous read port
|
|
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~
|
2023-04-04 04:31:26 -05:00
|
|
|
|
|
|
|
.. code:: verilog
|
|
|
|
|
|
|
|
reg [7:0] mem [0:255];
|
|
|
|
wire [7:0] write_addr;
|
|
|
|
wire [5:0] read_addr;
|
|
|
|
wire [7:0] write_data;
|
|
|
|
reg [31:0] read_data;
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if (write_enable)
|
|
|
|
mem[write_addr] <= write_data;
|
|
|
|
if (read_enable) begin
|
|
|
|
read_data[7:0] <= mem[{read_addr, 2'b00}];
|
|
|
|
read_data[15:8] <= mem[{read_addr, 2'b01}];
|
|
|
|
read_data[23:16] <= mem[{read_addr, 2'b10}];
|
|
|
|
read_data[31:24] <= mem[{read_addr, 2'b11}];
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
Wide asynchronous read port
|
|
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
|
|
|
|
- Note: the only target natively supporting this pattern is Xilinx UltraScale
|
|
|
|
|
|
|
|
.. code:: verilog
|
|
|
|
|
|
|
|
reg [7:0] mem [0:511];
|
|
|
|
wire [8:0] write_addr;
|
|
|
|
wire [5:0] read_addr;
|
|
|
|
wire [7:0] write_data;
|
|
|
|
wire [63:0] read_data;
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if (write_enable)
|
|
|
|
mem[write_addr] <= write_data;
|
|
|
|
end
|
|
|
|
|
|
|
|
assign read_data[7:0] = mem[{read_addr, 3'b000}];
|
|
|
|
assign read_data[15:8] = mem[{read_addr, 3'b001}];
|
|
|
|
assign read_data[23:16] = mem[{read_addr, 3'b010}];
|
|
|
|
assign read_data[31:24] = mem[{read_addr, 3'b011}];
|
|
|
|
assign read_data[39:32] = mem[{read_addr, 3'b100}];
|
|
|
|
assign read_data[47:40] = mem[{read_addr, 3'b101}];
|
|
|
|
assign read_data[55:48] = mem[{read_addr, 3'b110}];
|
|
|
|
assign read_data[63:56] = mem[{read_addr, 3'b111}];
|
|
|
|
|
|
|
|
Wide write port
|
|
|
|
~~~~~~~~~~~~~~~
|
|
|
|
|
|
|
|
.. code:: verilog
|
|
|
|
|
|
|
|
reg [7:0] mem [0:255];
|
|
|
|
wire [5:0] write_addr;
|
|
|
|
wire [7:0] read_addr;
|
|
|
|
wire [31:0] write_data;
|
|
|
|
reg [7:0] read_data;
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if (write_enable[0])
|
|
|
|
mem[{write_addr, 2'b00}] <= write_data[7:0];
|
|
|
|
if (write_enable[1])
|
|
|
|
mem[{write_addr, 2'b01}] <= write_data[15:8];
|
|
|
|
if (write_enable[2])
|
|
|
|
mem[{write_addr, 2'b10}] <= write_data[23:16];
|
|
|
|
if (write_enable[3])
|
|
|
|
mem[{write_addr, 2'b11}] <= write_data[31:24];
|
|
|
|
if (read_enable)
|
|
|
|
read_data <= mem[read_addr];
|
|
|
|
end
|
|
|
|
|
2023-06-18 19:05:51 -05:00
|
|
|
True dual port (TDP) patterns
|
|
|
|
-----------------------------
|
2023-04-04 04:31:26 -05:00
|
|
|
|
|
|
|
- Many different variations of true dual port memory can be created by combining two single-port RAM
|
|
|
|
patterns on the same memory
|
|
|
|
- When TDP memory is used, memory inference code has much less maneuver room to create requested
|
|
|
|
semantics compared to individual single-port patterns (which can end up lowered to SDP memory
|
|
|
|
where necessary) — supported patterns depend strongly on the target
|
|
|
|
- In particular, when both ports have the same clock, it's likely that "undefined collision" mode
|
|
|
|
needs to be manually selected to enable TDP memory inference
|
|
|
|
- The examples below are non-exhaustive — many more combinations of port types are possible
|
|
|
|
- Note: if two write ports are in the same process, this defines a priority relation between them
|
|
|
|
(if both ports are active in the same clock, the later one wins). On almost all targets, this will
|
|
|
|
result in a bit of extra circuitry to ensure the priority semantics. If this is not what you want,
|
|
|
|
put them in separate processes.
|
|
|
|
|
|
|
|
- Priority is not supported when using the verific front end and any priority semantics are ignored.
|
|
|
|
|
2023-06-18 19:05:51 -05:00
|
|
|
TDP with different clocks, exclusive read/write
|
|
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
2023-04-04 04:31:26 -05:00
|
|
|
|
|
|
|
.. code:: verilog
|
|
|
|
|
|
|
|
reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0];
|
|
|
|
|
|
|
|
always @(posedge clk_a) begin
|
|
|
|
if (write_enable_a)
|
|
|
|
mem[addr_a] <= write_data_a;
|
|
|
|
else if (read_enable_a)
|
|
|
|
read_data_a <= mem[addr_a];
|
|
|
|
end
|
|
|
|
|
|
|
|
always @(posedge clk_b) begin
|
|
|
|
if (write_enable_b)
|
|
|
|
mem[addr_b] <= write_data_b;
|
|
|
|
else if (read_enable_b)
|
|
|
|
read_data_b <= mem[addr_b];
|
|
|
|
end
|
|
|
|
|
2023-06-18 19:05:51 -05:00
|
|
|
TDP with same clock, read-first behavior
|
|
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
2023-04-04 04:31:26 -05:00
|
|
|
|
|
|
|
- This requires hardware inter-port read-first behavior, and will only work on some targets (Xilinx, Nexus)
|
|
|
|
|
|
|
|
.. code:: verilog
|
|
|
|
|
|
|
|
reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0];
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if (write_enable_a)
|
|
|
|
mem[addr_a] <= write_data_a;
|
|
|
|
if (read_enable_a)
|
|
|
|
read_data_a <= mem[addr_a];
|
|
|
|
end
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if (write_enable_b)
|
|
|
|
mem[addr_b] <= write_data_b;
|
|
|
|
if (read_enable_b)
|
|
|
|
read_data_b <= mem[addr_b];
|
|
|
|
end
|
|
|
|
|
2023-06-18 19:05:51 -05:00
|
|
|
TDP with multiple read ports
|
|
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
2023-04-04 04:31:26 -05:00
|
|
|
|
|
|
|
- The combination of a single write port with an arbitrary amount of read ports is supported on all
|
|
|
|
targets — if a multi-read port primitive is available (like Xilinx RAM64M), it'll be used as
|
|
|
|
appropriate. Otherwise, the memory will be automatically split into multiple primitives.
|
|
|
|
|
|
|
|
.. code:: verilog
|
|
|
|
|
|
|
|
reg [31:0] mem [0:31];
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if (write_enable)
|
|
|
|
mem[write_addr] <= write_data;
|
|
|
|
end
|
|
|
|
|
|
|
|
assign read_data_a = mem[read_addr_a];
|
|
|
|
assign read_data_b = mem[read_addr_b];
|
|
|
|
assign read_data_c = mem[read_addr_c];
|
|
|
|
|
2023-09-18 18:26:57 -05:00
|
|
|
Patterns only supported with Verific
|
|
|
|
------------------------------------
|
2023-04-04 04:31:26 -05:00
|
|
|
|
|
|
|
Synchronous SDP with write-first behavior via blocking assignments
|
|
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
|
2023-12-06 22:14:21 -06:00
|
|
|
- Use `sdp_wf`_ for compatibility with Yosys
|
2023-09-18 18:26:57 -05:00
|
|
|
Verilog frontend.
|
2023-04-04 04:31:26 -05:00
|
|
|
|
|
|
|
.. code:: verilog
|
|
|
|
|
|
|
|
reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0];
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if (write_enable)
|
|
|
|
mem[write_addr] = write_data;
|
|
|
|
|
|
|
|
if (read_enable)
|
|
|
|
read_data <= mem[read_addr];
|
|
|
|
end
|
|
|
|
|
|
|
|
Asymmetric memories via part selection
|
|
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
|
2023-12-06 22:14:21 -06:00
|
|
|
- Build wide ports out of narrow ports instead (see `wide_sr`_) for
|
|
|
|
compatibility with Yosys Verilog frontend.
|
2023-04-04 04:31:26 -05:00
|
|
|
|
|
|
|
.. code:: verilog
|
|
|
|
|
|
|
|
reg [31:0] mem [2**ADDR_WIDTH - 1 : 0];
|
|
|
|
|
|
|
|
wire [1:0] byte_lane;
|
|
|
|
wire [7:0] write_data;
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if (write_enable)
|
|
|
|
mem[write_addr][byte_lane * 8 +: 8] <= write_data;
|
|
|
|
|
|
|
|
if (read_enable)
|
|
|
|
read_data <= mem[read_addr];
|
|
|
|
end
|
|
|
|
|
|
|
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Undesired patterns
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------------------
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Asynchronous writes
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~~~~~~~~~~~~~~~~~~~
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- Not supported in modern FPGAs
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- Not supported in yosys code anyhow
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.. code:: verilog
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reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0];
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always @* begin
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if (write_enable)
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mem[write_addr] = write_data;
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end
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assign read_data = mem[read_addr];
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