yosys/manual/APPNOTE_011_Design_Investig.../foobaraddsub.v

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2013-11-29 09:42:49 -06:00
module foobaraddsub(a, b, c, d, fa, fs, ba, bs);
input [7:0] a, b, c, d;
output [7:0] fa, fs, ba, bs;
assign fa = a + (* foo *) b;
assign fs = a - (* foo *) b;
assign ba = c + (* bar *) d;
assign bs = c - (* bar *) d;
endmodule