mirror of https://github.com/YosysHQ/yosys.git
47 lines
2.5 KiB
Python
47 lines
2.5 KiB
Python
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#!/usr/bin/env python3
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def write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits):
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ada_conn = [".ADA%d(%s)" % (i, ada_bits[i]) for i in range(len(ada_bits))]
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adb_conn = [".ADB%d(%s)" % (i, adb_bits[i]) for i in range(len(adb_bits))]
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dia_conn = [".DIA%d(%s)" % (i, dia_bits[i]) for i in range(len(dia_bits))]
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dob_conn = [".DOB%d(%s)" % (i, dob_bits[i]) for i in range(len(dob_bits))]
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print(" %s," % ", ".join(ada_conn), file=f)
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print(" %s," % ", ".join(adb_conn), file=f)
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print(" %s," % ", ".join(dia_conn), file=f)
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print(" %s," % ", ".join(dob_conn), file=f)
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with open("techlibs/ecp5/bram_conn_1.vh", "w") as f:
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ada_bits = ["A1ADDR[%d]" % i for i in range(14)]
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adb_bits = ["B1ADDR[%d]" % i for i in range(14)]
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dia_bits = ["A1DATA[0]"] + ["1'b0" for i in range(17)]
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dob_bits = ["B1DATA[0]"]
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write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
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with open("techlibs/ecp5/bram_conn_2.vh", "w") as f:
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ada_bits = ["1'b0"] + ["A1ADDR[%d]" % i for i in range(13)]
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adb_bits = ["1'b0"] + ["B1ADDR[%d]" % i for i in range(13)]
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dia_bits = ["A1DATA[%d]" % i for i in range(2)] + ["1'b0" for i in range(16)]
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dob_bits = ["B1DATA[%d]" % i for i in range(2)]
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write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
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with open("techlibs/ecp5/bram_conn_4.vh", "w") as f:
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ada_bits = ["1'b0", "1'b0"] + ["A1ADDR[%d]" % i for i in range(12)]
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adb_bits = ["1'b0", "1'b0"] + ["B1ADDR[%d]" % i for i in range(12)]
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dia_bits = ["A1DATA[%d]" % i for i in range(4)] + ["1'b0" for i in range(14)]
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dob_bits = ["B1DATA[%d]" % i for i in range(4)]
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write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
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with open("techlibs/ecp5/bram_conn_9.vh", "w") as f:
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ada_bits = ["1'b0", "1'b0", "1'b0"] + ["A1ADDR[%d]" % i for i in range(11)]
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adb_bits = ["1'b0", "1'b0", "1'b0"] + ["B1ADDR[%d]" % i for i in range(11)]
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dia_bits = ["A1DATA[%d]" % i for i in range(9)] + ["1'b0" for i in range(9)]
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dob_bits = ["B1DATA[%d]" % i for i in range(9)]
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write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
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with open("techlibs/ecp5/bram_conn_18.vh", "w") as f:
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ada_bits = ["A1EN[0]", "A1EN[1]", "1'b0", "1'b0"] + ["A1ADDR[%d]" % i for i in range(10)]
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adb_bits = ["1'b0", "1'b0", "1'b0", "1'b0"] + ["B1ADDR[%d]" % i for i in range(10)]
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dia_bits = ["A1DATA[%d]" % i for i in range(18)]
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dob_bits = ["B1DATA[%d]" % i for i in range(18)]
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write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
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