mirror of https://github.com/YosysHQ/yosys.git
109 lines
3.0 KiB
C++
109 lines
3.0 KiB
C++
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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struct SplitnetsWorker
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{
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std::map<RTLIL::Wire*, std::vector<RTLIL::Wire*>> splitmap;
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void operator()(RTLIL::SigSpec &sig)
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{
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sig.expand();
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for (auto &c : sig.chunks)
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if (splitmap.count(c.wire) > 0) {
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c.wire = splitmap.at(c.wire).at(c.offset);
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c.offset = 0;
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}
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sig.optimize();
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}
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};
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struct SplitnetsPass : public Pass {
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SplitnetsPass() : Pass("splitnets", "split up multi-bit nets") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" splitnets [options] [selection]\n");
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log("\n");
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log("This command splits multi-bit nets into single-bit nets.\n");
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log("\n");
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log(" -ports\n");
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log(" also split module ports. per default only internal signals are split.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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bool flag_ports = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-ports") {
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flag_ports = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto &mod_it : design->modules)
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{
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RTLIL::Module *module = mod_it.second;
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if (!design->selected(module))
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continue;
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SplitnetsWorker worker;
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for (auto &w : module->wires) {
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RTLIL::Wire *wire = w.second;
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if (wire->width > 1 && (wire->port_id == 0 || flag_ports))
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worker.splitmap[wire] = std::vector<RTLIL::Wire*>();
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}
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for (auto &it : worker.splitmap)
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for (int i = 0; i < it.first->width; i++) {
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RTLIL::Wire *wire = new RTLIL::Wire;
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wire->port_id = it.first->port_id;
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wire->port_input = it.first->port_input;
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wire->port_output = it.first->port_output;
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wire->name = it.first->name + stringf("[%d]", i);
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while (module->count_id(wire->name) > 0)
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wire->name = wire->name + "_";
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module->add(wire);
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it.second.push_back(wire);
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}
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module->rewrite_sigspecs(worker);
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for (auto &it : worker.splitmap) {
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module->wires.erase(it.first->name);
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delete it.first;
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}
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module->fixup_ports();
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}
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}
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} SplitnetsPass;
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