yosys/tests/arch/microchip/reduce.ys

# ISC License
# 
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
# 
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# 
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

read_verilog <<EOT
module reduce(
	input [7:0] data,
	output Y
);
	assign Y = ^data;
endmodule
EOT
synth_microchip -top reduce -family polarfire -noiopad
select -assert-count 1 t:XOR8
select -assert-none t:XOR8 %% t:* %D