mirror of https://github.com/YosysHQ/yosys.git
21 lines
297 B
Verilog
21 lines
297 B
Verilog
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module top
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(
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input [4:0] x,
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input [4:0] y,
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output lt,
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output le,
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output gt,
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output ge,
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output eq,
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output ne
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);
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assign lt = x < y;
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assign le = x <= y;
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assign gt = x > y;
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assign ge = x >= y;
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assign eq = x == y;
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assign ne = x != y;
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endmodule
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