mirror of https://github.com/YosysHQ/yosys.git
64 lines
1.3 KiB
Bash
64 lines
1.3 KiB
Bash
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#!/bin/bash
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trap 'echo "ERROR in svalways.sh" >&2; exit 1' ERR
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# Good case
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../../yosys -f "verilog -sv" -qp proc - <<EOT
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module top(input clk, en, d, output reg p, q, r);
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always_ff @(posedge clk)
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p <= d;
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always_comb
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q = ~d;
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always_latch
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if (en) r = d;
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endmodule
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EOT
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# Incorrect always_comb syntax
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((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT
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module top(input d, output reg q);
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always_comb @(d)
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q = ~d;
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endmodule
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EOT
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) 2>&1 | grep -F "<stdin>:3: ERROR: syntax error, unexpected '@'" > /dev/null
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# Incorrect use of always_comb
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((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT
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module top(input en, d, output reg q);
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always_comb
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if (en) q = d;
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endmodule
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EOT
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) 2>&1 | grep -F "ERROR: Latch inferred for signal \`\\top.\\q' from always_comb process" > /dev/null
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# Incorrect use of always_latch
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((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT
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module top(input en, d, output reg q);
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always_latch
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q = !d;
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endmodule
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EOT
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) 2>&1 | grep -F "ERROR: No latch inferred for signal \`\\top.\\q' from always_latch process" > /dev/null
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# Incorrect use of always_ff
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((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT
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module top(input en, d, output reg q);
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always_ff @(*)
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q = !d;
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endmodule
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EOT
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) 2>&1 | grep -F "ERROR: Found non edge/level sensitive event in always_ff process" > /dev/null
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