mirror of https://github.com/YosysHQ/yosys.git
23 lines
384 B
Verilog
23 lines
384 B
Verilog
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module uut_always03(clock, in1, in2, in3, in4, in5, in6, in7, out1, out2, out3);
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input clock, in1, in2, in3, in4, in5, in6, in7;
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output out1, out2, out3;
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reg out1, out2, out3;
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always @(posedge clock) begin
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out1 = in1;
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if (in2)
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out1 = !out1;
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out2 <= out1;
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if (in3)
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out2 <= out2;
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if (in4)
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if (in5)
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out3 <= in6;
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else
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out3 <= in7;
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out1 = out1 ^ out2;
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end
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endmodule
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