mirror of https://github.com/YosysHQ/yosys.git
9 lines
240 B
Verilog
9 lines
240 B
Verilog
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module foobaraddsub(a, b, c, d, fa, fs, ba, bs);
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input [7:0] a, b, c, d;
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output [7:0] fa, fs, ba, bs;
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assign fa = a + (* foo *) b;
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assign fs = a - (* foo *) b;
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assign ba = c + (* bar *) d;
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assign bs = c - (* bar *) d;
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endmodule
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