mirror of https://github.com/YosysHQ/yosys.git
85 lines
2.5 KiB
C++
85 lines
2.5 KiB
C++
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* (C) 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct XilinxFinalisePass : public Pass
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{
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XilinxFinalisePass() : Pass("xilinx_finalise", "") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" xilinx_finalise [options]\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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break;
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}
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extra_args(args, argidx, design);
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log_header(design, "Executing XILINX_FINALISE pass.\n");
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for (auto module : design->selected_modules())
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for (auto cell : module->selected_cells()) {
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if (cell->type != ID(DSP48E1))
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continue;
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for (auto &conn : cell->connections_) {
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if (!cell->output(conn.first))
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continue;
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bool purge = true;
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for (auto &chunk : conn.second.chunks()) {
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auto it = chunk.wire->attributes.find(ID(unused_bits));
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if (it == chunk.wire->attributes.end())
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continue;
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std::string unused_bits = stringf("%d", chunk.offset);
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for (auto i = 1; i < chunk.width; i++)
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unused_bits += stringf(" %d", i+chunk.offset);
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if (it->second.decode_string().find(unused_bits) == std::string::npos) {
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purge = false;
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break;
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}
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}
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if (purge) {
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log_debug("Purging unused port connection %s %s (.%s(%s))\n", cell->type.c_str(), log_id(cell), log_id(conn.first), log_signal(conn.second));
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conn.second = SigSpec();
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}
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}
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}
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}
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} XilinxFinalisePass;
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PRIVATE_NAMESPACE_END
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