mirror of https://github.com/YosysHQ/yosys.git
150 lines
5.4 KiB
Coq
150 lines
5.4 KiB
Coq
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Pre Normalize ////
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//// Floating Point Pre Normalization Unit for FMUL ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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`timescale 1ns / 100ps
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module pre_norm_fmul(clk, fpu_op, opa, opb, fracta, fractb, exp_out, sign,
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sign_exe, inf, exp_ovf, underflow);
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input clk;
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input [2:0] fpu_op;
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input [31:0] opa, opb;
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output [23:0] fracta, fractb;
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output [7:0] exp_out;
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output sign, sign_exe;
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output inf;
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output [1:0] exp_ovf;
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output [2:0] underflow;
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////////////////////////////////////////////////////////////////////////
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//
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// Local Wires and registers
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//
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reg [7:0] exp_out;
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wire signa, signb;
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reg sign, sign_d;
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reg sign_exe;
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reg inf;
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wire [1:0] exp_ovf_d;
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reg [1:0] exp_ovf;
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wire [7:0] expa, expb;
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wire [7:0] exp_tmp1, exp_tmp2;
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wire co1, co2;
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wire expa_dn, expb_dn;
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wire [7:0] exp_out_a;
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wire opa_00, opb_00, fracta_00, fractb_00;
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wire [7:0] exp_tmp3, exp_tmp4, exp_tmp5;
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wire [2:0] underflow_d;
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reg [2:0] underflow;
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wire op_div = (fpu_op == 3'b011);
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wire [7:0] exp_out_mul, exp_out_div;
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////////////////////////////////////////////////////////////////////////
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//
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// Aliases
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//
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assign signa = opa[31];
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assign signb = opb[31];
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assign expa = opa[30:23];
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assign expb = opb[30:23];
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////////////////////////////////////////////////////////////////////////
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//
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// Calculate Exponenet
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//
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assign expa_dn = !(|expa);
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assign expb_dn = !(|expb);
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assign opa_00 = !(|opa[30:0]);
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assign opb_00 = !(|opb[30:0]);
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assign fracta_00 = !(|opa[22:0]);
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assign fractb_00 = !(|opb[22:0]);
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assign fracta = {!expa_dn,opa[22:0]}; // Recover hidden bit
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assign fractb = {!expb_dn,opb[22:0]}; // Recover hidden bit
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assign {co1,exp_tmp1} = op_div ? (expa - expb) : (expa + expb);
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assign {co2,exp_tmp2} = op_div ? ({co1,exp_tmp1} + 8'h7f) : ({co1,exp_tmp1} - 8'h7f);
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assign exp_tmp3 = exp_tmp2 + 1;
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assign exp_tmp4 = 8'h7f - exp_tmp1;
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assign exp_tmp5 = op_div ? (exp_tmp4+1) : (exp_tmp4-1);
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always@(posedge clk)
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exp_out <= #1 op_div ? exp_out_div : exp_out_mul;
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assign exp_out_div = (expa_dn | expb_dn) ? (co2 ? exp_tmp5 : exp_tmp3 ) : co2 ? exp_tmp4 : exp_tmp2;
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assign exp_out_mul = exp_ovf_d[1] ? exp_out_a : (expa_dn | expb_dn) ? exp_tmp3 : exp_tmp2;
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assign exp_out_a = (expa_dn | expb_dn) ? exp_tmp5 : exp_tmp4;
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assign exp_ovf_d[0] = op_div ? (expa[7] & !expb[7]) : (co2 & expa[7] & expb[7]);
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assign exp_ovf_d[1] = op_div ? co2 : ((!expa[7] & !expb[7] & exp_tmp2[7]) | co2);
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always @(posedge clk)
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exp_ovf <= #1 exp_ovf_d;
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assign underflow_d[0] = (exp_tmp1 < 8'h7f) & !co1 & !(opa_00 | opb_00 | expa_dn | expb_dn);
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assign underflow_d[1] = ((expa[7] | expb[7]) & !opa_00 & !opb_00) |
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(expa_dn & !fracta_00) | (expb_dn & !fractb_00);
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assign underflow_d[2] = !opa_00 & !opb_00 & (exp_tmp1 == 8'h7f);
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always @(posedge clk)
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underflow <= #1 underflow_d;
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always @(posedge clk)
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inf <= #1 op_div ? (expb_dn & !expa[7]) : ({co1,exp_tmp1} > 9'h17e) ;
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////////////////////////////////////////////////////////////////////////
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//
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// Determine sign for the output
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//
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// sign: 0=Posetive Number; 1=Negative Number
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always @(signa or signb)
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case({signa, signb}) // synopsys full_case parallel_case
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2'b0_0: sign_d = 0;
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2'b0_1: sign_d = 1;
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2'b1_0: sign_d = 1;
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2'b1_1: sign_d = 0;
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endcase
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always @(posedge clk)
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sign <= #1 sign_d;
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always @(posedge clk)
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sign_exe <= #1 signa & signb;
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endmodule
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