2019-08-21 13:52:07 -05:00
|
|
|
read_verilog div_mod.v
|
|
|
|
|
hierarchy -top top
|
2019-08-22 14:30:49 -05:00
|
|
|
flatten
|
2019-08-22 14:35:35 -05:00
|
|
|
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
2019-08-21 13:52:07 -05:00
|
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
|
|
|
cd top # Constrain all select calls below inside the top module
|
|
|
|
|
select -assert-count 88 t:SB_LUT4
|
|
|
|
|
select -assert-count 65 t:SB_CARRY
|
|
|
|
|
select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D
|
