yosys/tests/verilog/include_self.ys

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read_verilog include_self.v
select -assert-count 1 top/x
verilog: fix handling of nested ifdef directives - track depth so we know whether to consider higher-level elsifs - error on unmatched endif/elsif/else 2021-02-25 14:53:55 -06:00			`read_verilog include_self.v`
			`select -assert-count 1 top/x`