yosys/tests/verilog/func_arg_mismatch_3.ys

logger -expect error "Incompatible re-declaration of wire" 1
read_verilog -sv <<EOT
module top;
    function automatic integer f;
        input [1:0] inp;
        integer inp;
        f = inp;
    endfunction
    integer x, y;
    initial x = f(y);
endmodule
EOT
verilog: fix sizing of constant args for tasks/functions - Simplify synthetic localparams for normal calls to update their width - This step was inadvertently removed alongside `added_mod_children` - Support redeclaration of constant function arguments - `eval_const_function` never correctly handled this, but the issue was not exposed in the existing tests until the recent change to always attempt constant function evaluation when all-const args are used - Check asserts in const_arg_loop and const_func tests - Add coverage for width mismatch error cases 2021-02-21 13:45:21 -06:00			`logger -expect error "Incompatible re-declaration of wire" 1`
			`read_verilog -sv <<EOT`
			`module top;`
			`function automatic integer f;`
			`input [1:0] inp;`
			`integer inp;`
			`f = inp;`
			`endfunction`
			`integer x, y;`
			`initial x = f(y);`
			`endmodule`
			`EOT`