mirror of https://github.com/YosysHQ/yosys.git
19 lines
327 B
VHDL
19 lines
327 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity work is
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Port (
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a : in INTEGER range -5 to 10;
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b : out INTEGER range -6 to 11
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);
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end entity work;
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architecture Behavioral of work is
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begin
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process(a)
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begin
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b <= a;
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end process;
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end architecture Behavioral;
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