yosys/tests/verilog/prefix.ys

read_verilog -sv prefix.sv
hierarchy
proc
select -module top
async2sync
sat -verify -seq 1 -prove-asserts -show-all
verilog: fix multiple AST_PREFIX scope resolution issues - Root AST_PREFIX nodes are now subject to genblk expansion to allow them to refer to a locally-visible generate block - Part selects on AST_PREFIX member leafs can now refer to generate block items (previously would not resolve and raise an error) - Add source location information to AST_PREFIX nodes 2021-08-02 19:42:34 -05:00			`read_verilog -sv prefix.sv`
			`hierarchy`
			`proc`
			`select -module top`
tests: Run async2sync before sat and/or sim to handle $check cells Right now neither `sat` nor `sim` have support for the `$check` cell. For formal verification it is a good idea to always run either async2sync or clk2fflogic which will (in a future commit) lower `$check` to `$assert`, etc. While `sim` should eventually support `$check` directly, using `async2sync` is ok for the current tests that use `sim`, so this commit also runs `async2sync` before running sim on designs containing assertions. 2024-01-22 10:44:05 -06:00			`async2sync`
verilog: fix multiple AST_PREFIX scope resolution issues - Root AST_PREFIX nodes are now subject to genblk expansion to allow them to refer to a locally-visible generate block - Part selects on AST_PREFIX member leafs can now refer to generate block items (previously would not resolve and raise an error) - Add source location information to AST_PREFIX nodes 2021-08-02 19:42:34 -05:00			`sat -verify -seq 1 -prove-asserts -show-all`