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yosys/tests/verilog/.gitignore

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Setup tests/verilog properly
2020-05-11 12:30:20 -05:00
/*.log
/*.out
write_verilog: don't `assign` to a `reg`. Fixes #2035.
2024-04-03 03:01:58 -05:00
/*.err
Setup tests/verilog properly
2020-05-11 12:30:20 -05:00
/run-test.mk
Update .gitignore Signed-off-by: David Shah <dave@ds0.me>
2020-10-01 09:53:14 -05:00
/const_arst.v
/const_sr.v
fixup verilog doubleslash test - add generated doubleslash.v to .gitignore - ensure backend verilog can be read again
2021-12-30 01:06:23 -06:00
/doubleslash.v
write_verilog: don't `assign` to a `reg`. Fixes #2035.
2024-04-03 03:01:58 -05:00
/roundtrip_proc_1.v
/roundtrip_proc_2.v
/assign_to_reg.v