mirror of https://github.com/YosysHQ/yosys.git
23 lines
698 B
Verilog
23 lines
698 B
Verilog
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//-----------------------------------------------------
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// Design Name : mux_using_assign
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// File Name : mux_using_assign.v
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// Function : 2:1 Mux using Assign
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// Coder : Deepak Kumar Tala
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//-----------------------------------------------------
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module mux_using_assign(
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din_0 , // Mux first input
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din_1 , // Mux Second input
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sel , // Select input
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mux_out // Mux output
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);
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//-----------Input Ports---------------
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input din_0, din_1, sel ;
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//-----------Output Ports---------------
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output mux_out;
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//------------Internal Variables--------
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wire mux_out;
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//-------------Code Start-----------------
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assign mux_out = (sel) ? din_1 : din_0;
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endmodule //End Of Module mux
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