mirror of https://github.com/YosysHQ/yosys.git
20 lines
315 B
Coq
20 lines
315 B
Coq
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module test01(clk, wr_en, wr_addr, wr_value, rd_addr, rd_value);
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input clk, wr_en;
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input [3:0] wr_addr, rd_addr;
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input [7:0] wr_value;
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output reg [7:0] rd_value;
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reg [7:0] data [15:0];
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always @(posedge clk)
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if (wr_en)
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data[wr_addr] <= wr_value;
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always @(posedge clk)
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rd_value <= data[rd_addr];
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endmodule
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