yosys/tests/hana/test_simulation_always_18_t...

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2013-01-05 04:13:26 -06:00
module test (in1, in2, out);
input in1, in2;
output reg out;
always @ ( in1 or in2)
if(in1 > in2)
out = in1;
else
out = in2;
endmodule