yosys/tests/hana/test_intermout_exprs_condex...

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2013-01-05 04:13:26 -06:00
module test(in, out, en, vin1, vout1, en1);
input in, en, en1;
output out;
input [1:0] vin1;
output [1:0] vout1;
assign out = en ? in : 1'bz;
assign vout1 = en1 ? vin1 : 2'bzz;
endmodule