mirror of https://github.com/YosysHQ/yosys.git
15 lines
313 B
Coq
15 lines
313 B
Coq
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module MyCounter (clock, preset, updown, presetdata, counter);
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input clock, preset, updown;
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input [1: 0] presetdata;
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output reg [1:0] counter;
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always @(posedge clock)
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if(preset)
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counter <= presetdata;
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else
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if(updown)
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counter <= counter + 1;
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else
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counter <= counter - 1;
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endmodule
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