yosys/tests/hana/test_intermout_always_comb_...

12 lines
179 B
Coq
Raw Normal View History

2013-01-05 04:13:26 -06:00
module test(ctrl, in1, in2, out);
input ctrl;
input in1, in2;
output reg out;
always @ (ctrl or in1 or in2)
if(ctrl)
out = in1 & in2;
else
out = in1 | in2;
endmodule