mirror of https://github.com/YosysHQ/yosys.git
22 lines
644 B
Verilog
22 lines
644 B
Verilog
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//-----------------------------------------------------
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// Design Name : parity_using_assign
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// File Name : parity_using_assign.v
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// Function : Parity using assign
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// Coder : Deepak Kumar Tala
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//-----------------------------------------------------
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module parity_using_assign (
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data_in , // 8 bit data in
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parity_out // 1 bit parity out
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);
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output parity_out ;
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input [7:0] data_in ;
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wire parity_out ;
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assign parity_out = (data_in[0] ^ data_in[1]) ^
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(data_in[2] ^ data_in[3]) ^
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(data_in[4] ^ data_in[5]) ^
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(data_in[6] ^ data_in[7]);
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endmodule
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