mirror of https://github.com/YosysHQ/yosys.git
29 lines
469 B
Verilog
29 lines
469 B
Verilog
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(* techmap_celltype = "$mul" *)
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module mul_swap_ports (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire _TECHMAP_FAIL_ = A_WIDTH <= B_WIDTH;
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\$mul #(
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.A_SIGNED(B_SIGNED),
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.B_SIGNED(A_SIGNED),
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.A_WIDTH(B_WIDTH),
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.B_WIDTH(A_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(B),
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.B(A),
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.Y(Y)
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);
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endmodule
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