yosys/tests/arch/intel_alm/blockram.ys

read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 10 sync_ram_sdp
synth_intel_alm -family cyclonev -noiopad
cd sync_ram_sdp
select -assert-count 1 t:MISTRAL_M10K
select -assert-none t:MISTRAL_M10K %% t:* %D
intel_alm: direct M10K instantiation This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8. 2020-07-26 13:28:10 -05:00			`read_verilog ../common/blockram.v`
			`chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 10 sync_ram_sdp`
intel_alm: Add IO buffer insertion Signed-off-by: gatecat <gatecat@ds0.me> 2021-05-15 08:23:22 -05:00			`synth_intel_alm -family cyclonev -noiopad`
intel_alm: direct M10K instantiation This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8. 2020-07-26 13:28:10 -05:00			`cd sync_ram_sdp`
			`select -assert-count 1 t:MISTRAL_M10K`
			`select -assert-none t:MISTRAL_M10K %% t:* %D`