mirror of https://github.com/YosysHQ/yosys.git
13 lines
329 B
Verilog
13 lines
329 B
Verilog
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module MISTRAL_IB((* iopad_external_pin *) input PAD, output O);
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assign O = PAD;
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endmodule
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module MISTRAL_OB((* iopad_external_pin *) output PAD, input I);
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assign PAD = I;
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endmodule
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module MISTRAL_IO((* iopad_external_pin *) inout PAD, input I, input OE, output O);
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assign PAD = OE ? I : 1'bz;
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assign O = PAD;
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endmodule
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