mirror of https://github.com/YosysHQ/yosys.git
38 lines
1.8 KiB
Plaintext
38 lines
1.8 KiB
Plaintext
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set hdlin_ignore_full_case false
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set hdlin_ignore_parallel_case false
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set svf_ignore_unqualified_fsm_information true
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set hdlin_warn_on_mismatch_message "FMR_ELAB-115 FMR_VLOG-079 FMR_VLOG-091"
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read_verilog -container r -libname WORK -01 rtl/omsp_alu.v
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read_verilog -container r -libname WORK -01 rtl/omsp_and_gate.v
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read_verilog -container r -libname WORK -01 rtl/omsp_clock_gate.v
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read_verilog -container r -libname WORK -01 rtl/omsp_clock_module.v
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read_verilog -container r -libname WORK -01 rtl/omsp_clock_mux.v
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read_verilog -container r -libname WORK -01 rtl/omsp_dbg_hwbrk.v
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read_verilog -container r -libname WORK -01 rtl/omsp_dbg_uart.v
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read_verilog -container r -libname WORK -01 rtl/omsp_dbg.v
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read_verilog -container r -libname WORK -01 rtl/omsp_execution_unit.v
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read_verilog -container r -libname WORK -01 rtl/omsp_frontend.v
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read_verilog -container r -libname WORK -01 rtl/omsp_mem_backbone.v
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read_verilog -container r -libname WORK -01 rtl/omsp_multiplier.v
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read_verilog -container r -libname WORK -01 rtl/omsp_register_file.v
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read_verilog -container r -libname WORK -01 rtl/omsp_scan_mux.v
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read_verilog -container r -libname WORK -01 rtl/omsp_sfr.v
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read_verilog -container r -libname WORK -01 rtl/omsp_sync_cell.v
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read_verilog -container r -libname WORK -01 rtl/omsp_sync_reset.v
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read_verilog -container r -libname WORK -01 rtl/omsp_wakeup_cell.v
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read_verilog -container r -libname WORK -01 rtl/omsp_watchdog.v
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read_verilog -container r -libname WORK -01 rtl/openMSP430.v
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set_top r:/WORK/openMSP430
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read_verilog -container i -libname WORK -01 synth.v
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read_verilog -container i -technology_library -libname TECH_WORK -01 ../../techlibs/stdcells_sim.v
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read_verilog -container i -technology_library -libname TECH_WORK -01 sim_mul.v
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set_top i:/WORK/openMSP430
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source fsm_info.txt
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if ![verify] start_gui exit
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