mirror of https://github.com/YosysHQ/yosys.git
19 lines
577 B
Plaintext
19 lines
577 B
Plaintext
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r
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proc
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memory -nomap
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equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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#ERROR: Called with -verify and proof did fail!
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#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
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sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w1r
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select -assert-count 8 t:RAM16S4
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# other logic present that is not simple
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#select -assert-none t:RAM16S4 %% t:* %D
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