mirror of https://github.com/YosysHQ/yosys.git
14 lines
303 B
Verilog
14 lines
303 B
Verilog
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module test1(a, b, c, d, e, f, y);
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input [19:0] a, b, c;
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input [15:0] d, e, f;
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output [41:0] y;
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assign y = a*b + c*d + e*f;
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endmodule
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module test2(a, b, c, d, e, f, y);
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input [19:0] a, b, c;
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input [15:0] d, e, f;
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output [41:0] y;
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assign y = a*b + (c*d + e*f);
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endmodule
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