2019-12-12 19:44:37 -06:00
|
|
|
read_verilog ../common/lutram.v
|
|
|
|
|
hierarchy -top lutram_1w1r
|
2019-10-21 09:25:15 -05:00
|
|
|
proc
|
|
|
|
|
memory -nomap
|
|
|
|
|
equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin
|
|
|
|
|
memory
|
|
|
|
|
opt -full
|
|
|
|
|
|
|
|
|
|
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
2022-02-08 23:13:34 -06:00
|
|
|
sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
|
2019-10-21 09:25:15 -05:00
|
|
|
sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
|
|
|
|
|
|
|
|
|
|
design -load postopt
|
2019-12-12 19:44:37 -06:00
|
|
|
cd lutram_1w1r
|
2022-02-08 23:13:34 -06:00
|
|
|
select -assert-count 8 t:RAM16SDP4
|
2019-10-21 09:25:15 -05:00
|
|
|
# other logic present that is not simple
|
|
|
|
|
#select -assert-none t:RAM16S4 %% t:* %D
|
