2020-11-17 13:35:17 -06:00
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read_verilog ../common/dffs.v
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design -save read
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hierarchy -top dff
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proc
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equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dff # Constrain all select calls below inside the top module
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select -assert-count 1 t:FACADE_FF
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select -assert-none t:FACADE_FF %% t:* %D
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2020-11-20 17:16:45 -06:00
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design -load read
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hierarchy -top dffe
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proc
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equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffe # Constrain all select calls below inside the top module
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select -assert-count 2 t:FACADE_FF t:LUT4
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select -assert-none t:FACADE_FF t:LUT4 %% t:* %D
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