mirror of https://github.com/YosysHQ/yosys.git
51 lines
1.1 KiB
Verilog
51 lines
1.1 KiB
Verilog
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module top(clk);
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parameter DEPTH_LOG2 = 10;
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parameter WIDTH = 36;
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parameter PRIME = 237481091;
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localparam DEPTH = 2**DEPTH_LOG2;
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input wire clk;
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(* syn_ramstyle = "block_ram" *)
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reg [WIDTH-1:0] mem [DEPTH-1:0];
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integer i;
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initial begin
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for (i = 0; i < DEPTH; i = i + 1) begin
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// Make up data by multiplying a large prime with the address,
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// then cropping and retaining the lower bits
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mem[i] = PRIME * i;
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end
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end
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reg [DEPTH_LOG2-1:0] counter = 0;
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reg done = 1'b0;
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reg did_read = 1'b0;
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reg [DEPTH_LOG2-1:0] read_addr;
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reg [WIDTH-1:0] read_val;
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always @(posedge clk) begin
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if (!done) begin
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did_read <= 1'b1;
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read_addr <= counter;
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read_val <= mem[counter];
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end else begin
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did_read <= 1'b0;
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end
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if (!done)
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counter = counter + 1;
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if (counter == 0)
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done = 1;
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end
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wire [WIDTH-1:0] expect_val = PRIME * read_addr;
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always @(posedge clk) begin
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if (did_read) begin
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$display("addr %x expected %x actual %x", read_addr, expect_val, read_val);
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assert(read_val == expect_val);
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end
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end
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endmodule
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