yosys/tests/arch/microchip/dsp.ys

# ISC License
# 
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
# 
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
# 
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

# pre-adder
design -reset
read_verilog <<EOT
module pre_adder(
	input signed [5:0] in_A,
	input signed [4:0] in_B,
	input signed [4:0] in_D,
	output [11:0] out_Y
);
    assign out_Y = in_A * (in_B + in_D);
endmodule
EOT
synth_microchip -top pre_adder -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D

# post-adder
design -reset
read_verilog <<EOT
module post_adder(
	input signed[17:0] in_A,
	input signed [17:0] in_B,
	input signed [17:0] in_C,
	output signed [35:0] out_Y
);
    assign out_Y = (in_B*in_A)+in_C;
endmodule
EOT
synth_microchip -top post_adder -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D

# pre-adder + post-adder
design -reset
read_verilog <<EOT
module pre_post_adder(
	input signed[5:0] in_A,
	input signed [4:0] in_B,
	input signed [11:0] in_C,
	input signed [4:0] in_D,
	output signed [12:0] out_Y
);
assign out_Y = ((in_D + in_B)*in_A)+in_C;
endmodule
EOT
synth_microchip -top pre_post_adder -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D


# multiply accumulate
design -reset
read_verilog <<EOT
module mac(
	input clk,
	input signed [4:0] in_A,
	input signed [4:0] in_B,
	input signed [4:0] in_D,
	input srst_P,
	output reg signed [11:0] out_P
);
	always@(posedge clk) begin
		if (~srst_P) begin
			out_P <= 12'h000;
		end else begin
			out_P <= in_A * (in_B + in_D) + out_P;
		end
	end
endmodule
EOT
synth_microchip -top mac -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D


# cascade
design -reset
read_verilog <<EOT
module cas(
	input signed [5:0] in_A,
	input signed [4:0] in_B,
	input signed [4:0] in_D,
	input signed [4:0] casA,
	input signed [4:0] casB,
	output signed [11:0] out_P
);
	wire signed [9:0] cascade;
	assign cascade = casA * casB;
	assign out_P = in_A * (in_B + in_D) + cascade;
endmodule
EOT
synth_microchip -top cas -family polarfire -noiopad
select -assert-count 2 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D

# carryout
design -reset
read_verilog <<EOT
module carryout (cout,out,a, b,c);
parameter n = 6;
parameter k = 2;
output reg [k*(n+1)-1:0] out;
output reg cout;
input [n:0] a;
input [n:0] b;
input [n-1:0] c;
	always @(*) 
	begin
		{cout,out} = a * b + c;
	end
endmodule
EOT
synth_microchip -top carryout -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D

# pipeline registers
design -reset
read_verilog <<EOT
module pipeline(
	input clk,
	input srst_A,
	input srst_B,
	input srst_D,
	input srst_P,
	input arst_D,
	input srst_C,
	input signed [5:0] in_A,
	input signed [4:0] in_B,
	input signed [4:0] in_C,
	input signed [4:0] in_D,
	output reg [11:0] out_P
);
wire srst_A_N;
wire srst_B_N;
wire srst_C_N;
wire srst_D_N;
wire srst_P_N;
assign srst_A_N = ~srst_A;
assign srst_B_N = ~srst_B;
assign srst_C_N = ~srst_C;
assign srst_D_N = ~srst_D;
assign srst_P_N = ~srst_P;

reg signed [5:0] reg_A;
reg signed [4:0] reg_B;
reg signed [4:0] reg_C;
reg signed [4:0] reg_D;

always@(posedge clk) begin // sync reset A
	// if (~srst_A_N) begin
	if (srst_A_N) begin
		reg_A = 6'b000000;
	end else begin
		reg_A = in_A;
	end
end

always@(posedge clk) begin // sync reset B
	if (srst_B_N) begin
		reg_B = 5'b00000;
	end else begin
		reg_B = in_B;
	end
end

always@(posedge clk, negedge arst_D) begin // async reset D
	if (~arst_D) begin
		reg_D = 5'b00000;
	end else begin
		reg_D = in_D;
	end
end

always@(posedge clk) begin // sync reset C
	if (srst_C_N) begin
		reg_C = 5'b00000;
	end else begin
		reg_C = in_C;
	end
end

// sync reset P
always@(posedge clk) begin
	if (srst_P_N) begin
		out_P = 12'h000;
	end else begin
		out_P = reg_A * (reg_B + reg_D) + reg_C;
	end
end
endmodule
EOT
synth_microchip -top pipeline -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D