yosys/tests/arch/microchip/dff_opt.ys

# ISC License
# 
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
# 
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
# 
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.


# reset can be merged into D LUT
read_verilog <<EOT
module dff_opt(
	input clk,
	input [1:0] D_comb,
	input [1:0] EN_comb,
	input [1:0] RST_comb,
	output bar
);
reg foo;
assign bar = foo;
always@(posedge clk) begin
	if (&RST_comb) begin
		foo <= 0;
	end else begin
		foo <= &D_comb;
	end
end
endmodule
EOT
synth_microchip -top dff_opt -family polarfire -noiopad
select -assert-count 1 t:SLE
select -assert-count 1 t:CFG4
select -assert-count 1 t:CLKBUF
select -assert-none t:SLE t:CFG4 t:CLKBUF %% t:* %D