mirror of https://github.com/YosysHQ/yosys.git
6 lines
138 B
Plaintext
6 lines
138 B
Plaintext
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read_verilog abc_01.v
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read_verilog -lib abc_01_cells.v
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hierarchy -check -top test
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proc; opt; techmap
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abc -dff -liberty abc_01_cells.lib;;
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