yosys/tests/simple/memwr_port_connection.sv

module producer(
    output logic [3:0] out
);
    assign out = 4'hA;
endmodule

module top(
    output logic [3:0] out
);
    logic [3:0] v[0:0];
    producer p(v[0]);
    assign out = v[0];
endmodule
verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change 2021-10-19 19:46:26 -05:00			`module producer(`
			`output logic [3:0] out`
			`);`
			`assign out = 4'hA;`
			`endmodule`

			`module top(`
			`output logic [3:0] out`
			`);`
			`logic [3:0] v[0:0];`
			`producer p(v[0]);`
			`assign out = v[0];`
			`endmodule`