mirror of https://github.com/YosysHQ/yosys.git
37 lines
857 B
Verilog
37 lines
857 B
Verilog
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module RAM_CLOCK_SDP(
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input CLK_CLK,
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input PORT_R_CLK,
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input [9:0] PORT_R_ADDR,
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output reg [15:0] PORT_R_RD_DATA,
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input PORT_W_CLK,
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input PORT_W_WR_EN,
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input [9:0] PORT_W_ADDR,
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input [15:0] PORT_W_WR_DATA
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);
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parameter INIT = 0;
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parameter PORT_R_WIDTH = 1;
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parameter PORT_W_WIDTH = 1;
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parameter CLK_CLK_POL = 0;
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parameter PORT_R_CLK_POL = 0;
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parameter PORT_W_CLK_POL = 0;
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parameter OPTION_WCLK = "ANY";
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parameter OPTION_RCLK = "ANY";
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reg [2**10-1:0] mem = INIT;
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wire RCLK;
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case (OPTION_RCLK)
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"ANY": assign RCLK = PORT_R_CLK == PORT_R_CLK_POL;
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"POS": assign RCLK = PORT_R_CLK;
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"NEG": assign RCLK = ~PORT_R_CLK;
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endcase
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always @(posedge RCLK)
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PORT_R_RD_DATA <= mem[PORT_R_ADDR+:PORT_R_WIDTH];
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always @(negedge PORT_W_CLK ^ (PORT_W_CLK_POL || OPTION_WCLK == "POS"))
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if (PORT_W_WR_EN)
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mem[PORT_W_ADDR+:PORT_W_WIDTH] <= PORT_W_WR_DATA;
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endmodule
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