mirror of https://github.com/YosysHQ/yosys.git
10 lines
186 B
Plaintext
10 lines
186 B
Plaintext
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read_verilog <<EOT
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module top(input i, output o);
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assign o = i;
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endmodule
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EOT
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design -stash foo
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design -delete foo
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logger -expect error "No saved design 'foo' found!" 1
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design -load foo
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